1. Technical Field
The present invention relates to network interfacing and more particularly to a network interface for efficiently supplying data from a buffer memory to a host bus.
2. Background Art
Network interface devices are commonly used to transmit data between a host computer and network communication systems, such as a local area network. Typical network interface devices include Ethernet-type and IEEE 802.3. One of the primary functions of a network interface is to control the transfer of data between a buffer and the host bus. The data stored in the buffer is retrieved as a result of one of two types of requests, namely master and slave.
In master mode, a transfer is initiated by a master device which must arbitrate for use of the host bus with a host CPU prior to retrieving the data. In slave mode, the host CPU provides a target device with sufficient information to access the buffer and retrieve the data. A slave access can be performed using two different types of mapping, namely memory mapping and Input/Output (I/O) mapping.
Transmission of data from the buffer memory to the host bus has traditionally been accomplished by providing specific logic for each type of request. FIG. 9 is a block diagram illustrating a typical buffer architecture 200 for accessing data from buffer memory. An interface unit 202 receives master and slave requests to access the buffer memory 204. The request is directed to a transfer logic 206 that transfers data to or from the buffer memory 204. The transfer logic 206 must be capable of handling each type of request individually. Thus, the interface unit 202 transfers the request to a specific logic portion in the transfer logic 206 based on the nature of the request. For example, the transfer logic 206 includes a first logic circuit 208 that services a master request, a second logic circuit 210 that services an I/O mapped slave request, and a third logic circuit 212 that services memory mapped slave requests.
Hence, a primary disadvantage associated with current methods of transferring data is the excessive amount of logic necessary to service the different types of requests. Another disadvantage is the increased latency encountered during the data transfer process. This latency can be defined as the delay between the time when data is retrieved from the buffer to the time it is delivered to the host bus. As previously mentioned, additional delays are encountered during transfers initiated by a master device, because the master device must arbitrate for access to the bus with other master devices that also require use of the bus.